Three-dimensional (3D) stacking with through-silicon vias (TSVs) is gaining considerable traction in the semiconductor industry due to its benefits over traditional stacking with wire-bonds. Unlike wire-bonds, TSVs go directly through the substrate, consuming relatively little silicon area and allowing for high-performance, high-density, and low-power inter-die connections in integrated circuits (ICs).
Testing of 3D ICs for manufacturing defects pose major challenges for the semiconductor industry. One of these challenges involves defects, such as voids and pinholes, from the TSV manufacturing process. Voids are formed due to insufficient filling of a via. A pinhole is an oxide defect that creates a short between the TSV and the substrate. Many of these defects arise prior to the bonding process. Therefore, they can be targeted during pre-bond testing, increasing the probability of getting a known good die (KGD) prior to bonding and therefore increasing the product yield. It has been widely acknowledged that the lack of KGD can be a serious yield limiter for 3D stacking.
However, pre-bond testing of TSVs can be difficult due to test access limitations. First, prior to wafer thinning, TSVs are buried in silicon and are only accessible at their front-side through the logic connected to the TSVs. Second, even though the back-side of a TSV is exposed after wafer thinning, probing the back-side can be challenging because of strict requirements on the probing equipment. Recent studies report success in mechanical probing at array pitches of 40 μm; however, such probing solutions are still being researched and it remains to be seen how easily they can be used in practice. Therefore, alternative solutions that do not rely on probing are being investigated.